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FEATURES Infinite Sample-and-Hold Capability to 0.018% Accuracy Infinite Sample-and-Hold Total Unadjusted Error 2.5 m V High Integration: 32-Channel DAC in 12 mm 12 mm CSPBGA Per Channel Acquisition Time of 16 s Max Adjustable Voltage Output Range Output Impedance 0.5 Output Voltage Span 10 V Readback Capability DSP/Microcontroller Compatible Serial Interface Parallel Interface Temperature Range -40 C to +85 C APPLICATIONS Optical Networks Automatic Test Equipment Level Setting Instrumentation Industrial Control Systems Data Acquisition Low Cost I/O
32-Channel Precision Infinite Sample-and-Hold AD5533B*
GENERAL DESCRIPTION
The AD5533B combines a 32-channel voltage translation function with an infinite output hold capability. An analog input voltage on the common input pin, VIN, is sampled and its digital representation transferred to a chosen DAC register. VOUT for this DAC is then updated to reflect the new contents of the DAC register. Channel selection is accomplished via the parallel address inputs A0-A4 or via the serial input port. The output voltage range is determined by the offset voltage at the OFFS_IN pin and the gain of the output amplifier. It is restricted to a range from VSS + 2 V to VDD - 2 V because of the headroom of the output amplifier. The device is operated with AVCC = +5 V 5%, DVCC = +2.7 V to +5.25 V, VSS = -4.75 V to -16.5 V, and VDD = +8 V to +16.5 V and requires a stable 3 V reference on REF_IN as well as an offset voltage on OFFS_IN.
PRODUCT HIGHLIGHTS
1. Precision infinite droopless sample-and-hold capability. 2. The AD5533B is available in a 74-lead CSPBGA with a body size of 12 mm 12 mm. 3. In infinite sample-and-hold mode, a total unadjusted error of 2.5 mV is achieved by laser-trimming on-chip resistors.
FUNCTIONAL BLOCK DIAGRAM
DVCC AVCC REF IN REF OUT OFFS IN VDD VSS
VOUT 0 VIN TRACK / RESET BUSY DAC GND AGND DAC DGND INTERFACE CONTROL LOGIC VOUT 31 ADC DAC
AD5533B
DAC OFFS OUT
SER / PAR
ADDRESS INPUT REGISTER
WR
SCLK DIN DOUT
SYNC/CS
A4 -A0
CAL
OFFSET SEL
*Protected by U.S. Patent No. 5,969,657; other patents pending.
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002
2.7 V to 5.25 V; REF_IN AD5533B-SPECIFICATIONS DV All=specificationsV;TAGND = DGND = DAC_GND = 0noted.) = 3 V; OFFS_IN = 0 V; Output Range from V + 2 V to V - 2 V. All outputs unloaded. to T , unless otherwise
CC SS DD MIN MAX
(VDD = +8 V to +16.5 V, VSS = -4.75 V to -16.5 V; AVCC = +4.75 V to +5.25 V;
Parameter1 ANALOG CHANNEL VIN to VOUT Nonlinearity
Total Unadjusted Error (TUE)
B Version2 0.006 0.018 3.51/3.52/3.53
1 10
Unit % typ % max
mV typ mV max
Conditions/Comments Input Range 100 mV to 2.96 V After Gain and Offset Adjustment
See TPC 6.
2.5 12
Gain Offset Error ANALOG INPUT (VIN) Input Voltage Range Input Lower Dead Band Input Upper Dead Band Input Current Input Capacitance3 ANALOG INPUT (OFFS_IN) Input Voltage Range Input Current VOLTAGE REFERENCE REF_IN Nominal Input Voltage Input Voltage Range3 Input Current REF_OUT Output Voltage Output Impedance3 Reference Temperature Coefficient3 ANALOG OUTPUTS (VOUT 0-31) Output Temperature Coefficient3, 4 DC Output Impedance Output Range Resistive Load3, 5 Capacitive Load3, 5 Short-Circuit Current3 DC Power Supply Rejection Ratio3 DC Crosstalk3 ANALOG OUTPUT (OFFS_OUT) Output Temperature Coefficient3, 4 DC Output Impedance3 Output Range Output Current Capacitive Load DIGITAL INPUTS3 Input Current Input Low Voltage Input High Voltage Input Hysteresis (SCLK and CS Only) Input Capacitance
min/typ/max mV typ mV max V mV max mV max A max pF typ V min/max A max
See TPC 2.
0 to 3 70 40 1 20 0/4 1
Nominal Input Range 50 mV typ. Referred to VIN. See Figure 5. 12 mV typ. Referred to VIN. See Figure 5. 100 nA typ. VIN acquired on one channel.
Output Range Restricted from VSS + 2 V to VDD - 2 V 100 nA typ
3.0 2.85/3.15 1 3 280 60 10 0.5 VSS + 2/VDD - 2 5 100 7 -70 -70 250 10 1.3 50 to REF_IN - 12 10 100 10 0.8 0.4 2.4 2.0 200 10
V V min/max A max V typ
k typ
<1 nA typ
ppm/C typ ppm/C typ
typ
V min/max
k min
100 A Output Load
pF max mA typ dB typ dB typ V max ppm/C typ
k typ
VDD = +15 V 5% VSS = -15 V 5% Outputs Loaded
mV typ A max pF max A max V max V max V min V min mV typ pF max
Source Current
5 A typ DVCC = 5 V DVCC = 3 V DVCC = 5 V DVCC = 3 V
5% 10% 5% 10%
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REV. A
AD5533B
Parameter1 DIGITAL OUTPUTS (BUSY, DOUT) Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage High Impedance Leakage Current High Impedance Output Capacitance POWER REQUIREMENTS Power Supply Voltages VDD VSS AVCC DVCC Power Supply Currents6 IDD ISS AICC DICC Power Dissipation6
3
B Version2 0.4 4.0 0.4 2.4 1 15
Unit V max V min V max V min A max pF typ
Conditions/Comments DVCC = 5 V. Sinking 200 A. DVCC = 5 V. Sourcing 200 A. DVCC = 3 V. Sinking 200 A. DVCC = 3 V. Sourcing 200 A. DOUT Only DOUT Only
8/16.5 -4.75/-16.5 4.75/5.25 2.7/5.25 15 15 33 1.5 280
V min/max V min/max V min/max V min/max mA max mA max mA max mA max mW typ 10 mA typ. All channels full-scale. 10 mA typ. All channels full-scale. 26 mA typ 1 mA typ VDD = +10 V, VSS = -5 V
NOTES 1 See Terminology section. 2 B Version: Industrial temperature range -40C to +85C; typical at +25C. 3 Guaranteed by design and characterization, not production tested. 4 AD780 as reference for the AD5533B. 5 Ensure that you do not exceed T J (max). See Absolute Maximum Ratings. 6 Outputs unloaded. Specifications subject to change without notice.
(VDD = +8 V to +16.5 V, VSS = -4.75 V to -16.5 V; AVCC = +4.75 V to +5.25 V; DVCC = +2.7 V to +5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = 3 V; OFFS_IN = 0 V; Output Range from VSS + 2 V to VDD - 2 V. All outputs unloaded. All specifications TMIN to TMAX, unless otherwise noted.)
AC CHARACTERISTICS
Parameter
2
B Version1 3 16 10 0.2 400 5
Unit s max s max s max nV-s typ nV/Hz typ nV-s typ
Conditions/Comments
Output Settling Time Acquisition Time OFFS_IN Settling Time2 Digital Feedthrough2 Output Noise Spectral Density @ 1 kHz2 AC Crosstalk2
500 pF, 5 k Load; 0 V-3 V Step
NOTES 1 B version: Industrial temperature range -40C to +85C; typical at 25C. 2 Guaranteed by design and characterization, not production tested. Specifications subject to change without notice.
REV. A
-3-
AD5533B TIMING CHARACTERISTICS
PARALLEL INTERFACE
Parameter1, 2 t1 t2 t3 t4 t5 t6
Limit at TMIN, TMAX (B Version) 0 0 50 50 20 7
Unit ns min ns min ns min ns min ns min ns min
Conditions/Comments CS to WR Setup Time CS to WR Hold Time CS Pulsewidth Low WR Pulsewidth Low A4-A0, CAL, OFFS_SEL to WR Setup Time A4-A0, CAL, OFFS_SEL to WR Hold Time
NOTES 1 See Parallel Interface Timing Diagram. 2 Guaranteed by design and characterization, not production tested. Specifications subject to change without notice.
SERIAL INTERFACE
Parameter1, 2 fCLKIN t1 t2 t3 t4 t5 t6 t7 t8 3 t9 3 t10 t114
Limit at TMIN, TMAX (B Version) 20 20 20 15 50 10 5 5 20 60 400 7
Unit MHz max ns min ns min ns min ns min ns min ns min ns min ns max ns max ns min ns min
Conditions/Comments SCLK Frequency SCLK High Pulsewidth SCLK Low Pulsewidth SYNC Falling Edge to SCLK Falling Edge Setup Time SYNC Low Time DIN Setup Time DIN Hold Time SYNC Falling Edge to SCLK Rising Edge Setup Time for Readback SCLK Rising Edge to DOUT Valid SCLK Falling Edge to DOUT High Impedance 10th SCLK Falling Edge to SYNC Falling Edge for Readback SCLK Falling Edge to SYNC Falling Edge Setup Time for Readback
NOTES 1 See Serial Interface Timing Diagrams. 2 Guaranteed by design and characterization, not production tested. 3 These numbers are measured with the load circuit of Figure 2. 4 SYNC should be taken low while SCLK is low for readback. Specifications subject to change without notice.
PARALLEL INTERFACE TIMING DIAGRAM
CS
TO OUTPUT PIN
200 A
IOL
WR
1.6V CL 50pF 200 A IOH
A4-A0, CAL, OFFS SEL
Figure 1. Parallel Write (ISHA Mode Only)
Figure 2. Load Circuit for DOUT Timing Specifications
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REV. A
AD5533B
SERIAL INTERFACE TIMING DIAGRAMS
t1
SCLK 1 2 3 4 5 6 7 8 9 10
t3
SYNC
t2
t4
t5 t6
DIN MSB LSB
Figure 3. 10-Bit Write (ISHA Mode and Both Readback Modes)
t7
SCLK
t1
1 2 3 4 5 6 7 8 9 10 11 12 13 14
10
t11
SYNC
t2
t10
DOUT MSB
t4
t8
t9
LSB
Figure 4. 14-Bit Read (Both Readback Modes)
REV. A
-5-
AD5533B
ABSOLUTE MAXIMUM RATINGS 1, 2
(TA = 25C, unless otherwise noted.)
Max Continuous Load Current at TJ = 70C, per Channel Group . . . . . . . . . . . . . . . . . . . . . . . 15.5 mA4
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operationa l sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latch-up. 3 This limit includes load power. 4 This maximum allowed continuous load current is spread over eight channels, with channels grouped as follows: Group 1: Channels 3, 4, 5, 6, 7, 8, 9, 10 Group 2: Channels 14, 16, 18, 20, 21, 24, 25, 26 Group 3: Channels 15, 17, 19, 22, 23, 27, 28, 29 Group 4: Channels 0, 1, 2, 11, 12, 13, 30, 31 For higher junction temperatures, derate as follows: Max Continuous Load Current per Group (mA) 15.5 9.025 6.925 5.175 3.425 2.55 1.5
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +17 V VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to -17 V AVCC to AGND, DAC_GND . . . . . . . . . . . . . -0.3 V to +7 V DVCC to DGND . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V Digital Inputs to DGND . . . . . . . . . . -0.3 V to DVCC + 0.3 V Digital Outputs to DGND . . . . . . . . . -0.3 V to DVCC + 0.3 V REF_IN to AGND, DAC_GND . . . . -0.3 V to AVCC + 0.3 V VIN to AGND, DAC_GND . . . . . . . . -0.3 V to AVCC + 0.3 V VOUT0-31 to AGND . . . . . . . . . . VSS - 0.3 V to VDD + 0.3 V OFFS_IN to AGND . . . . . . . . . . VSS - 0.3 V to VDD + 0.3 V OFFS_OUT to AGND . . . . AGND - 0.3 V to AVCC + 0.3 V AGND to DGND . . . . . . . . . . . . . . . . . . . . -0.3 V to +0.3 V Operating Temperature Range Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Junction Temperature (TJ max) . . . . . . . . . . . . . . . . . . 150C 74-Lead CSPBGA Package, JA Thermal Impedance . . 41C/W Reflow Soldering Peak Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 220C Time at Peak Temperature . . . . . . . . . . . . 10 sec to 40 sec Max Power Dissipation . . . . . . . . . . . . (150C - TA)/JA mW3
TJ (C) 70 90 100 110 125 135 150
ORDERING GUIDE
Description AD5533BBC-1 AD5533ABC-1* AD5532ABC-1* AD5532ABC-2* AD5532ABC-3* AD5532ABC-5* AD5532BBC-1* EVAL-AD5533EB
*Separate Data Sheet
Function 32-Channel Precision ISHA Only 32-Channel ISHA Only 32 DACs, 32-Channel ISHA 32 DACs, 32-Channel ISHA 32 DACs, 32-Channel ISHA 32 DACs, 32-Channel ISHA 32 DACs, 32-Channel Precision ISHA AD5532/AD5533 Evaluation Board
Output Impedance (Typ) 0.5 0.5 0.5 0.5 500 1 k 0.5
Output Voltage Span Package (V) Description 10 10 10 20 10 10 10 74-Lead CSPBGA 74-Lead CSPBGA 74-Lead CSPBGA 74-Lead CSPBGA 74-Lead CSPBGA 74-Lead CSPBGA 74-Lead CSPBGA
Package Option BC-74 BC-74 BC-74 BC-74 BC-74 BC-74 BC-74
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5533B features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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REV. A
AD5533B
PIN CONFIGURATION
1 2 3 4 5 6 7 8 9 10 11
A B C D E F G H J K L
A B C D E F G H J K L
1
2
3
4
5
6
7
8
9
10 11
74-Lead CSPBGA Ball Configuration
CSPBGA Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 C1 C2 C6
Ball Name NC* A4 A2 A0 CS/SYNC DVCC SCLK OFFSET_SEL BUSY TRACK/RESET NC* VO16 NC* A3 A1 WR DGND DIN CAL SER/PAR DOUT REF_IN VO18 DAC_GND1 NC*
CSPBGA Number C10 C11 D1 D2 D10 D11 E1 E2 E10 E11 F1 F2 F10 F11 G1 G2 G10 G11 H1 H2 H10 H11 J1 J2 J6
Ball Name AVCC1 REF_OUT VO20 DAC_GND2 AVCC2 OFFS_OUT VO26 VO14 AGND1 OFFS_IN VO25 VO21 AGND2 VO6 VO24 VO8 VO5 VO3 VO23 VIN VO4 VO7 VO22 VO19 VSS2
CSPBGA Number J10 J11 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11
Ball Name VO9 VO11 VO17 VO15 VO27 VSS3 VSS1 VSS4 VDD2 VO2 VO10 VO13 VO12 NC* VO28 VO29 VO30 VDD3 VDD1 VDD4 VO31 VO0 VO1 NC*
*NC = Not Connected
REV. A
-7-
AD5533B
PIN FUNCTION DESCRIPTIONS
Pin AGND (1-2) AVCC (1-2) VDD (1-4) VSS (1-4) DGND DVCC DAC_GND (1-2) REF_IN REF_OUT VOUT (0-31) VIN A4-A11, A02 CAL1 CS/SYNC WR1 OFFSET_SEL1 SCLK2 DIN2 DOUT SER/PAR1 OFFS_IN OFFS_OUT BUSY TRACK/RESET2
Function Analog GND Pins Analog Supply Pins. Voltage range from 4.75 V to 5.25 V. VDD Supply Pins. Voltage range from 8 V to 16.5 V. VSS Supply Pins. Voltage range from -4.75 V to -16.5 V. Digital GND Pins Digital Supply Pins. Voltage range from 2.7 V to 5.25 V. Reference GND Supply for all the DACs Reference Voltage for Channels 0-31 Reference Output Voltage Analog Output Voltages from the 32 Channels Analog Input Voltage Parallel Interface. 5-address pins for 32 channels. A4 = MSB of channel address. A0 = LSB. Parallel Interface. Control input that allows all 32 channels to acquire VIN simultaneously. This pin is both the active low chip select pin for the parallel interface and the frame synchronization pin for the serial interface. Parallel Interface. Write pin. Active low. This is used in conjunction with the CS pin to address the device using the parallel interface. Parallel Interface. Offset select pin. Active high. This is used to select the offset channel. Serial Clock Input for Serial Interface. This operates at clock speeds up to 20 MHz. Data Input for Serial Interface. Data must be valid on the falling edge of SCLK. Output from the DAC Registers for Readback. Data is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK. This pin allows the user to select whether the serial or parallel interface will be used. If the pin is tied low, the parallel interface will be used. If it is tied high, the serial interface will be used. Offset Input. The user can supply a voltage here to offset the output span. OFFS_OUT can also be tied to this pin if the user wants to drive this pin with the offset channel. Offset Output. This is the acquired/programmed offset voltage that can be tied to the OFFS_IN pin to offset the span. This output tells the user when the input voltage is being acquired. It goes low during acquisition and returns high when the acquisition operation is complete. If this input is held high, VIN is acquired once the channel is addressed. While it is held low, the input to the gain/offset stage is switched directly to VIN. The addressed channel begins to acquire VIN on the rising edge of TRACK. See TRACK Input section for further information. This input can also be used as a means of resetting the complete device to its power-on-reset conditions. This is achieved by applying a low going pulse of between 90 ns and 200 ns to this pin. See section on RESET Function for further details.
NOTES 1 Internal pull-down devices on these logic inputs. Therefore, they can be left floating and will default to a logic low condition. 2 Internal pull-up devices on these logic inputs. Therefore, they can be left floating and will default to a logic high condition.
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REV. A
AD5533B
TERMINOLOGY VIN to VOUT Nonlinearity DC Power Supply Rejection Ratio
This is a measure of the maximum deviation from a straight line passing through the endpoints of the VIN versus VOUT transfer function. It is expressed as a percentage of the full-scale span.
Total Unadjusted Error (TUE)
DC Power Supply Rejection Ratio (PSRR) is a measure of the change in analog output for a change in supply voltage (VDD and VSS). It is expressed in dBs. VDD and VSS are varied 5%.
DC Crosstalk
This is a comprehensive specification that includes relative accuracy, gain, and offset errors. It is measured by sampling a range of voltages on VIN and comparing the measured voltages on VOUT to the ideal value. It is expressed in mV.
Offset Error
This is the dc change in the output level of one channel in response to a full-scale change in the output of all other channels. It is expressed in V.
Output Settling Time
This is the time taken from when BUSY goes high to when the output has settled to 0.018%.
Acquisition Time
This is a measure of the output error when VIN = 70 mV. Ideally, with VIN = 70 mV:
VOUT = (Gain x 70) - ((Gain - 1) x VOFFS _ IN ) mV
Offset error is a measure of the difference between VOUT (actual) and VOUT (ideal). It is expressed in mV and can be positive or negative. See Figure 5.
Gain Error
This is the time taken for the VIN input to be acquired. It is the length of time that BUSY stays low.
OFFS_IN Settling Time
This is the time taken from a 0 V-3 V step change in input voltage on OFFS_IN until the output has settled to within 0.39%.
Digital Feedthrough
This is a measure of the span error of the analog channel. It is the deviation in slope of the transfer function. See Figure 5. It is calculated as:
Gain Error = Actual Full- Scale Output - Ideal Full- Scale Output Offset - Error
where
This is a measure of the impulse injected into the analog outputs from the digital control inputs when the part is not being written to, i.e., CS/SYNC is high. It is specified in nV-secs and is measured with a worst-case change on the digital input pins, e.g., from all 0s to all 1s and vice versa.
Output Noise Spectral Density
Ideal Full- Scale Output = (Gain x 2.96) - ((Gain - 1) x VOFFS _ IN )
Ideal Gain = 3.52
Output Temperature Coefficient
This is a measure of internally generated random noise. Random noise is characterized as a spectral density (voltage per root Hertz). It is measured by acquiring 1.5 V on all channels and measuring noise at the output. It is measured in nV/Hz typ.
AC Crosstalk
This is a measure of the change in analog output with changes in temperature. It is expressed in ppm/C.
This is the area of the glitch that occurs on the output of one channel while another channel is acquiring. It is expressed in nV-secs.
VOUT GAIN ERROR + OFFSET ERROR IDEAL TRANSFER FUNCTION
OFFSET ERROR
ACTUAL TRANSFER FUNCTION
0V
70mV
2.96
3V
VIN
LOWER DEAD BAND
UPPER DEAD BAND
Figure 5. ISHA Transfer Function
REV. A
-9-
AD5533B-Typical Performance Characteristics
0.0024 0.0020 0.0016 0.0012 TA = 25 C VREFIN = 3V VOFFS_IN = 0V
5V
100 90
BUSY
VOUT ERROR - V
0.0008 0.0004 0.0000 -0.0004 -0.0008 -0.0012 -0.0016 -0.0020 -0.0024 0.1 VIN - V 2.96
10 0%
VOUT
TA = 25 C VREFIN = 3V VIN = 0V TO 1.5V
1V
2s
TPC 1. VIN to VOUT Accuracy After Offset and Gain Adjustment
TPC 4. Acquisition Time and Output Settling Time
4
3.530
70k TA = 25 C VREFIN = 3V VIN = 1.5V VOFFS_IN = 0V 63791
60k 3 3.525
OFFSET ERROR - mV
GAIN
50k
FREQUENCY
2
3.520
GAIN
40k
30k
OFFSET ERROR 1 3.515
20k
10k 200 0 -40 0 40 TEMPERATURE - C 80 3.500 120 0 5.2670 5.2676 VOUT - V 1545 5.2682
TPC 2. Offset Error and Gain vs. Temperature
TPC 5. ISHA Mode Repeatability (64 K Acquisitions)
3.530 TA = 25 C VREFIN = 3V VIN = 1V
40
3.525
FREQUENCY
VOUT - V
20
3.520
3.515
6
4
2 0 -2 SINK/SOURCE CURRENT - mA
-4
-6
0
-4
-3
-2
-1 0 1 2 3 4 5 TOTAL UNADJUSTED ERROR - mV
6
7
8
TPC 3. VOUT Source and Sink Capability
TPC 6. TUE Distribution at 25C (ISHA Mode)
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REV. A
AD5533B
FUNCTIONAL DESCRIPTION
ADDRESSED CHANNEL VIN C1 20pF C2 7.5pF
The AD5533B can be thought of as consisting of an ADC and 32 DACs in a single package. The input voltage VIN is sampled and converted into a digital word. The digital result is loaded into one of the DAC registers and is converted (with gain and offset) into an analog output voltage (VOUT0-VOUT31). Since the channel output voltage is effectively the output of a DAC there is no droop associated with it. As long as power to the device is maintained, the output voltage will remain constant until this channel is addressed again. To update a single channel's output voltage, the required new voltage level is set up on the common input pin, VIN. The desired channel is then addressed via the parallel port or the serial port. When the channel address has been loaded, provided TRACK is high, the circuit begins to acquire the correct code to load to the DAC so that the DAC output matches the voltage on VIN. The BUSY pin goes low and remains so until the acquisition is complete. The noninverting input to the output buffer is tied to VIN during the acquisition period to avoid spurious outputs while the DAC acquires the correct code. The acquisition is completed in 16 s max. The BUSY pin goes high and the updated DAC output assumes control of the output voltage. The output voltage of the DAC is connected to the noninverting input of the output buffer. Since the internal DACs are offset by 70 mV (max) from GND, the minimum VIN in ISHA mode is 70 mV. The maximum VIN is 2.96 V due to the upper dead band of 40 mV (max). On power-on, all the DACs, including the offset channel, are loaded with zeros. Each of the 33 DACs is offset internally by 50 mV (typ) from GND so the outputs VOUT0 to VOUT31 are 50 mV (typ) on power-on if the OFFS_IN pin is driven directly by the on-board offset channel (OFFS_OUT), i.e., if OFFS_IN = OFFS_OUT = 50 mV = > VOUT = (Gain VDAC) - (Gain - 1) VOFFS_IN = 50 mV.
Analog Input
Figure 6. Analog Input Circuit
Large source impedances will significantly affect the performance of the ADC. This may necessitate the use of an input buffer amplifier.
Output Buffer Stage--Gain and Offset
The function of the output buffer stage is to translate the 50 mV-3 V typical output of the DAC to a wider range. This is done by gaining up the DAC output by 3.52 and offsetting the voltage by the voltage on OFFS_IN pin.
VOUT = 3.52 x VDAC - 2.52 x VOFFS_IN
VDAC is the output of the DAC. VOFFS_IN is the voltage at the OFFS_IN pin. Table I shows how the output range on VOUT relates to the offset voltage supplied by the user.
Table I. Sample Output Voltage Ranges
VOFFS_IN (V) 0 1 2.130
VDAC (V) 0.05 to 3 0.05 to 3 0.05 to 3
VOUT (V) 0.176 to 10.56 -2.34 to +8.04 -5.192 to +5.192
VOUT is limited only by the headroom of the output amplifiers. VOUT must be within maximum ratings.
Offset Voltage Channel
The equivalent analog input circuit is shown in Figure 6. The capacitor C1 is typically 20 pF and can be attributed to pin capacitance and 32 off-channels. When a channel is selected, an extra 7.5 pF (typ) is switched in. This capacitor C2 is charged to the previously acquired voltage on that particular channel so it must charge/discharge to the new level. It is essential that the external source can charge/discharge this additional capacitance within 1 s-2 s of channel selection so that VIN can be acquired accurately. For this reason, a low impedance source is recommended.
The offset voltage can be externally supplied by the user at OFFS_IN or it can be supplied by an additional offset voltage channel on the device itself. The required offset voltage is set up on VIN and acquired by the offset DAC. This offset channel's DAC output is directly connected to OFFS_OUT. By connecting OFFS_OUT to OFFS_IN, this offset voltage can be used as the offset voltage for the 32 output amplifiers. It is important to choose the offset so that VOUT is within maximum ratings.
PIN DRIVER VIN CONTROLLER CONTROLLER DAC BUSY TRACK OUTPUT STAGE VOUT1 DEVICE UNDER TEST
ACQUISITION ACQUISITION CIRCUIT CIRCUIT
AD5533B
THRESHOLD VOLTAGE ONLY ONE CHANNEL SHOWN FOR SIMPLICITY
Figure 7. Typical ATE Circuit Using TRACK Input
REV. A
-11-
AD5533B
Reset Function 1. ISHA Mode
The reset function on the AD5533B can be used to reset all nodes on this device to their power-on-reset condition. This is implemented by applying a low-going pulse of between 90 ns and 200 ns to the TRACK/RESET pin on the device. If the applied pulse is less than 90 ns, it is assumed to be a glitch and no operation takes place. If the applied pulse is wider than 200 ns, this pin adopts its track function on the selected channel, VIN is switched to the output buffer, and an acquisition on the channel will not occur until a rising edge of TRACK.
TRACK Function
In this standard mode, a channel is addressed and that channel acquires the voltage on VIN. This mode requires a 10-bit write (see Figure 3) to address the relevant channel (VOUT0-VOUT31, offset channel, or all channels). MSB is written first.
2. Acquire and Readback Mode
Normally in ISHA mode of operation, TRACK is held high and the channel begins to acquire when it is addressed. However, if TRACK is low when the channel is addressed, VIN is switched to the output buffer and an acquisition on the channel will not occur until a rising edge of TRACK. At this stage the BUSY pin will go low until the acquisition is complete, at which point the DAC assumes control of the voltage to the output buffer and VIN is free to change again without affecting this output value. This is useful in an application where the user wants to ramp up VIN until VOUT reaches a particular level (Figure 7). VIN does not need to be acquired continuously while it is ramping up. TRACK can be kept low and only when VOUT has reached its desired voltage is TRACK brought high. At this stage, the acquisition of VIN begins. In the example shown, a desired voltage is required on the output of the pin driver. This voltage is represented by one input to a comparator. The microcontroller/microprocessor ramps up the input voltage on VIN through a DAC. TRACK is kept low while the voltage on VIN ramps up so that VIN is not continually acquired. When the desired voltage is reached on the output of the pin driver, the comparator output switches. The C/P then knows what code is required to be input in order to obtain the desired voltage at the DUT. The TRACK input is now brought high and the part begins to acquire VIN. BUSY goes low until VIN has been acquired. When BUSY goes high, the output buffer is switched from VIN to the output of the DAC.
MODES OF OPERATION
This mode allows the user to acquire VIN and read back the data in a particular DAC register. The relevant channel is addressed (10-bit write, MSB first) and VIN is acquired in 16 s (max). Following the acquisition, after the next falling edge of SYNC, the data in the relevant DAC register is clocked out onto the DOUT line in a 14-bit serial format (see Figure 4). During readback, DIN is ignored. The full acquisition time must elapse before the DAC register data can be clocked out.
3. Readback Mode
Again, this is a readback mode but no acquisition is performed. The relevant channel is addressed (10-bit write, MSB first) and on the next falling edge of SYNC, the data in the relevant DAC register is clocked out onto the DOUT line in a 14-bit serial format (see Figure 4). The user must allow 400 ns (min) between the last SCLK falling edge in the 10-bit write and the falling edge of SYNC in the 14-bit readback. The serial write and read words can be seen in Figure 8. This feature allows the user to read back the DAC register code of any of the channels. Readback is useful if the system has been calibrated and the user wants to know what code in the DAC corresponds to a desired voltage on VOUT.
INTERFACES Serial Interface
The SER/PAR pin is tied high to enable the serial interface and to disable the parallel interface. The serial interface is controlled by four pins as follows:
SYNC, DIN, SCLK
Standard 3-wire interface pins. The SYNC pin is shared with the CS function of the parallel interface.
DOUT
The AD5533B can be used in three different modes. These modes are set by two mode bits, the first two bits in the serial word. The 01 option (DAC Mode) is not available for the AD5533B. For information on this mode, refer to the AD5532B data sheet. If you attempt to set up DAC Mode, the AD5533B will enter a test mode and a 24-clock write will be necessary to clear this.
Table II. Modes of Operation
Data out pin for reading back the contents of the DAC registers. The data is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK.
Mode Bits
There are four different modes of operation as described above.
Cal Bit
Mode Bit 1 0 0 1 1
Mode Bit 2 0 1 0 1
Operating Mode ISHA Mode DAC Mode (Not Available) Acquire and Readback Readback
When this is high, all 32 channels acquire VIN simultaneously. The acquisition time is then 45 s (typ) and accuracy may be reduced. This bit is set low for normal operation.
Offset_Sel Bit
If this bit is set high, the offset channel is selected and bits A4-A0 are ignored.
Test Bit
This must be set low for correct operation of the part.
A4-A0 Bit
Used to address any one of the 32 channels (A4 = MSB of address, A0 = LSB).
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REV. A
AD5533B
MSB 0 MODE BIT 1 0 MODE BIT 2 CAL OFFSET SEL 0 TEST BIT LSB A4-A0
MODE BITS
a. 10-Bit Input Serial Write Word (ISHA Mode)
MSB 1 0 CAL OFFSET SEL 0 TEST BIT MODE BITS 10-BIT SERIAL WORD WRITTEN TO PART 14-BIT DATA READ FROM PART AFTER NEXT FALLING EDGE OF SYNC (DB13 = MSB OF DAC WORD) LSB A4-A0 MSB DB1 3 -DB0 LSB
b. Input Serial Interface (Acquire and Readback Mode)
MSB 1 1 0 OFFSET SEL 0 TEST BIT MODE BITS 10-BIT SERIAL WORD WRITTEN TO PART 14-BIT DATA READ FROM PART AFTER NEXT FALLING EDGE OF SYNC (DB13 = MSB OF DAC WORD) LSB A4-A0 MSB DB1 3 -DB0 LSB
c. Input Serial Interface (Readback Mode) Figure 8. Serial Interface Formats
DB13-DB0 Bit
Parallel Interface
These are used in both readback modes to read a 14-bit word from the addressed DAC register. The serial interface is designed to allow easy interfacing to most microcontrollers and DSPs, e.g., PIC16C, PIC17C, QSPITM, SPITM, DSP56000, TMS320, and ADSP-21xx, without the need for any glue logic. When interfacing to the 8051, the SCLK must be inverted. The Microprocessor/Microcontroller Interface section explains how to interface to some popular DSPs and microcontrollers. Figures 3 and 4 show the timing diagram for a serial read and write to the AD5533B. The serial interface works with both a continuous and a noncontinuous serial clock. The first falling edge of SYNC resets a counter that counts the number of serial clocks to ensure the correct number of bits are shifted in and out of the serial shift registers. Any further edges on SYNC are ignored until the correct number of bits are shifted in or out. Once the correct number of bits have been shifted in or out, the SCLK is ignored. In order for another serial transfer to take place, the counter must be reset by the falling edge of SYNC. In readback, the first rising SCLK edge after the falling edge of SYNC causes DOUT to leave its high impedance state and data is clocked out onto the DOUT line and also on subsequent SCLK rising edges. The DOUT pin goes back into a high impedance state on the falling edge of the 14th SCLK. Data on the DIN line is latched in on the first SCLK falling edge after the falling edge of the SYNC signal and on subsequent SCLK falling edges. The serial interface will not shift data in or out until it receives the falling edge of the SYNC signal.
*SPI and QSPI are trademarks of Motorola, Inc.
The SER/PAR bit is tied low to enable the parallel interface and disable the serial interface. The parallel interface is controlled by nine pins as follows:
CS
Active low package select pin. This pin is shared with the SYNC function for the serial interface.
WR
Active low write pin. The values on the address pins are latched on a rising edge of WR.
A4-A0
Five address pins (A4 = MSB of address, A0 = LSB). These are used to address the relevant channel (out of a possible 32).
Offset_Sel
Offset select pin. This has the same function as the Offset_Sel bit in the serial interface. When it is high, the offset channel is addressed and the address on A4-A0 is ignored.
Cal
Same functionality as the Cal bit in the serial interface. When this pin is high, all 32 channels acquire VIN simultaneously.
MICROPROCESSOR INTERFACING AD5533B to ADSP-21xx Interface
The ADSP-21xx family of DSPs is easily interfaced to the AD5533B without the need for extra logic. A data transfer is initiated by writing a word to the TX register after the SPORT has been enabled. In a write sequence, data is clocked out on each rising edge of the DSP's serial clock and clocked into the AD5533B on the falling edge of its SCLK. In
REV. A
-13-
AD5533B
readback, 16 bits of data are clocked out of the AD5533B on each rising edge of SCLK and clocked into the DSP on the rising edge of SCLK. DIN is ignored. The valid 14 bits of data will be centered in the 16-bit RX register when using this configuration. The SPORT control register should be set up as follows: TFSW INVRFS DTYPE ISCLK TFSR IRFS ITFS SLEN SLEN = RFSW = 1, Alternate Framing = INVTFS = 1, Active Low Frame Signal = 00, Right-Justify Data = 1, Internal Serial Clock = RFSR = 1, Frame Every Word = 0, External Framing Signal = 1, Internal Framing Signal = 1001, 10-Bit Data-Words (ISHA Mode Write) = 1111, 16-Bit Data-Words (Readback Mode)
AD5533B to PIC16C6x/7x
The PIC16C6x synchronous serial port (SSP) is configured as an SPI Master with the clock polarity bit = 0. This is done by writing to the Synchronous Serial Port Control Register (SSPCON). See PIC16/17 Microcontroller User Manual. In this example I/O port RA1 is being used to pulse SYNC and enable the serial port of the AD5533B. This microcontroller transfers only eight bits of data during each serial transfer operation; therefore, two consecutive read/write operations are needed for a 10-bit write and a 14-bit readback. Figure 11 shows the connection diagram.
AD5533B*
SCLK DOUT DIN SYNC
PIC16C6x/7x*
SCK/RC3 SDO/RC5 SDI/RC4 RA1
Figure 9 shows the connection diagram.
AD5533B*
DOUT SYNC DR TFS RFS DIN SCLK *ADDITIONAL PINS OMITTED FOR CLARITY DT SCLK
ADSP-2101/ ADSP-2103*
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 11. AD5533B to PIC16C6x/7x Interface
AD5533B to 8051
Figure 9. AD5533B to ADSP-2101/ADSP-2103 Interface
AD5533B to MC68HC11
The serial peripheral interface (SPI) on the MC68HC11 is configured for master mode (MSTR = 1), clock polarity bit (CPOL) = 0 and the clock phase bit (CPHA) = 1. The SPI is configured by writing to the SPI control register (SPCR)-- see 68HC11 User Manual. SCK of the 68HC11 drives the SCLK of the AD5533B, the MOSI output drives the serial data line (DIN) of the AD5533B, and the MISO input is driven from DOUT. The SYNC signal is derived from a port line (PC7). When data is being transmitted to the AD5533B, the SYNC line is taken low (PC7). Data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. In order to transmit 10 data bits in ISHA mode it is important to left-justify the data in the SPDR register. PC7 must be pulled low to start a transfer. It is taken high and pulled low again before any further read/write cycles can take place. A connection diagram is shown in Figure 10.
AD5533B*
DOUT SYNC SCLK DIN *ADDITIONAL PINS OMITTED FOR CLARITY MISO PC7 SCK MOSI
The AD5533B requires a clock synchronized to the serial data. The 8051 serial interface must therefore be operated in Mode 0. In this mode, serial data enters and exits through RxD and a shift clock is output on TxD. Figure 12 shows how the 8051 is connected to the AD5533B. Because the AD5533B shifts data out on the rising edge of the shift clock and latches data in on the falling edge, the shift clock must be inverted. The AD5533B requires its data with the MSB first. Since the 8051 outputs the LSB first, the transmit routine must take this into account.
AD5533B*
SCLK DOUT DIN SYNC *ADDITIONAL PINS OMITTED FOR CLARITY P1.1 TXD RXD
8051*
Figure 12. AD5533B to 8051 Interface
APPLICATION CIRCUITS AD5533B in a Typical ATE System
MC68HC11*
The AD5533B infinite sample-and-hold is ideally suited for use in automatic test equipment. Several ISHAs are required to control pin drivers, comparators, active loads, and signal timing. Traditionally, sample-and-hold devices with droop were used in these applications. These required refreshing to prevent the voltage from drifting. The AD5533B has several advantages: no refreshing is required, there is no droop, pedestal error is eliminated, and there is no need for extra filtering to remove glitches. Overall, a higher level of integration is achieved in a smaller area. See Figure 13.
Figure 10. AD5533B to MC68HC11 Interface
-14-
REV. A
AD5533B
PARAMETRIC MEASUREMENT SYSTEM BUS UNIT ISHA ISHA ISHA ACTIVE LOAD
POWER SUPPLY DECOUPLING
STORED DATA AND INHIBIT PATTERN FORMATTER
DRIVER ISHA
ISHA PERIOD GENERATION AND DELAY TIMING
DUT
ISHA COMPARE REGISTER ISHA COMPARATOR
ISHAs
SYSTEM BUS
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5533B is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5533B is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device. For supplies with multiple pins (VSS, VDD, AVCC) it is recommended to tie those pins together. The AD5533B should have ample supply bypassing of 10 F in parallel with 0.1 F on each supply located as close to the package as possible, ideally right up against the device. The 10 F capacitors are the tantalum bead type. The 0.1 F capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), like the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. The power supply lines of the AD5533B should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. A ground line routed between the DIN and SCLK lines will help reduce crosstalk between them (not required on a multilayer board as there will be a separate ground plane, but separating the lines will help). It is essential to minimize noise on VIN and REFIN lines. Note it is essential to minimize noise on VIN and REFIN lines. Particularly for optimum ISHA performance, the VIN line must be kept noise-free. Depending on the noise performance of the board, a noise filtering capacitor may be required on the VIN line. If this capacitor is necessary, then for optimum throughput it may be necessary to buffer the source that is driving VIN. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best, but not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side. As is the case for all thin packages, care must be taken to avoid flexing the CSPBGA package and to avoid a point load on the surface of this package during the assembly process.
Figure 13. AD5533B in an ATE System
Typical Application Circuit
The AD5533B can be used to set up voltage levels on 32 channels as shown in the circuit below. An AD780 provides the 3 V reference for the AD5533B, and for the AD5541 16-bit DAC. A simple 3-wire serial interface is used to write to the AD5541. Because the AD5541 has an output resistance of 6.25 k (typ), the time taken to charge/ discharge the capacitance at the VIN pin is significant. Thus an AD820 is used to buffer the DAC output. Note that it is important to minimize noise on VIN and REFIN when laying out this circuit.
AVCC AVCC DVCC VSS
VDD
CS DIN SCLK
AD5541*
AD820
VIN
AD5533B*
REF OFFS_IN OFFS_OUT REFIN
VOUT 0-31
AD780*
VOUT SCLK DIN *ADDITIONAL PINS OMITTED FOR CLARITY SYNC
Figure 14. Typical Application Circuit
REV. A
-15-
AD5533B
OUTLINE DIMENSIONS 74-Lead Chip Scale Ball Grid Array [CSPBGA] (BC-74)
Dimensions shown in millimeters
A1 CORNER INDEX AREA
11 10 9 8 7 6 5 4 3 2 1
A1
TOP VIEW
1.00 BSC
BOT TOM VIEW
A B C D E F G H J K L
10.00 BSC SQ
1.00 BSC 1.70 MAX DETAIL A
DETAIL A
0.30 MIN 0.20 MAX COPLANARITY 0.70 SEATING 0.60 PLANE 0.50 BALL DIAMETER COMPLIANT TO JEDEC STANDARDS MO-192ABD-1
Revision History
Location 9/02--Data Sheet changed from REV. 0 to REV. A. Page
Term LFBGA updated to CSPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Replaced FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Additions to SERIAL INTERFACE Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Replaced Figure 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Additions to POWER SUPPLY DECOUPLING section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Updated BC-74 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
-16-
REV. A
PRINTED IN U.S.A.
C02715-0-9/02(A)
12.00 BSC SQ

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